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data brief for further information contact your local stmicroelectronics sales office. march 2009 rev 3 1/20 20 sta2058 teseo? gps platform high-s ensitivity baseband features single chip baseband with embedded flash complete embedded memory system: ? flash 256 kb +16 kbytes ? ram 64 kbytes 66 mhz arm7tdmi 32 bit processor high performance gps engine (hpgps) sbas (waas and egnos) supported sensitivity (-146 dbm acquisition, -159 dbm tracking) time to first fix (1s reacquisition, 2.5 s hot start, 34 s warm start, 39 s cold start) accuracy (2 m autonomous) external memory interface (emi) supporting up to 64 mbite of external sram, flash and rom extensive gps receiver interfaces: 48 gpios, 4 uarts, 2 spis, 2 i2cs, 2 cans 2.0, 1 usb 1.1,1 hdlc and 4 channels adc st proprietary flash embedded technology lfbga144 and lqfp64 lead-free package -40 c to 85 c operating temperature range evaluation kits sta2058 module reference design (25x25mm) evaluation board hosting sta2058 module sdk board (for application sw development) description sta2058 is the high-sensitivity baseband of teseo gps platform whic h include the sta5620 rf front-end. the embedded flash memory enables the equipment manufacturer to load the entire gps software (including tracking, acquisition, navigation and data output) after customizing its interfaces to his needs. a standard gps library is available from st. teseo is the ideal so lution for consumer, handheld, pnd (portable navigation), in vehicle navigation and telematics systems. sbas (waas and egnos) feature is also supported. lqfp64 lfbga144 table 1. device summary order code package emi (external memory interface) packing automotive grade sta2058 lqfp64 (10x10x1.4mm) no tray no sta2058tr lqfp64 (10x10x1.4mm) no tape and reel no sta2058ex lfbga144 (10x10x1.7mm) yes tray no STA2058EXTR lfbga144 (10x10x1.7mm) yes tape and reel no sta2058exa lfbga144 (10x10x1.7mm) yes tray yes sta2058exatr lfbga144 (10x10x1.7mm) yes tape and reel yes www.st.com
contents sta2058 2/20 contents 1 features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 package lfbga144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 package lqfp64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 dc electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 nrstin input filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 flash electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 pll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 lvd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.9 gps performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
sta2058 features summary 3/20 1 features summary arm7tdmi 16/32 bit risc cpu based host mi crocontroller running at a frequency up to 66 mhz. complete embedded memory system: ? flash 256 kbytes + 16 kbytes (100 kb erasing/programming cycles) ? ram 64 kbytes. external memory interface provides glueless support for up to four banks of external sram, flash, rom. high performance gps engine (hpgps). st proprietary cmos (0.18 m) flash embedded technology. sbas (waas and egnos) supported -40 c to 85 c operating temperature range. 144-pin lfbga package and 64-pin lqfp package power supply: ? 3.0 v to 3.6 v operating supply range for input/output periphery ? 3.0 v to 3.6 v operating supply range for a/d converter reference ? 1.8 v operating supply range for core supply provided either by internal voltage regulator (with external st abilization capacitor) or by external supply voltage. reset and clock control unit able to provide low power modes (wait, slow, stop, standby) and to generate the internal clock from the external reference through integrated pll. 48 programmable general purpose i/o, each pin programmable independently as digital input or digital output; 40 (30 in lqfp64) are multiplexed with peripheral functions; 16 can generate an interrupt on input level/transition. real time clock module with 32 khz low powe r oscillator and separate power supply to continue running during standby mode. 16-bit watchdog timer with 8 bits presca ler for system reliability and integrity. 2 can modules compliant with the can specific ation v2.0 part b (active) and bit rate can be programmed up to 1 mbaud. one additional can at 1 mbps (for sta2058 em sip version) four 16-bit programmable timers with 7 bit prescaler, up to two input capture/output compare, one pulse counter function, one pwm channel with selectable frequency each. 4 channels 12-bit sigma-delta analog to digital converter, single channel or multi channel conversion modes, single-shot or continuous conversion modes, sample rate 1 khz, conversion range 0-2.5 v . three serial communication interfaces (uart) allow full duplex, asynchronous, communications with external devices, independently programmable tx and rx baud rates up to 625 kbaud. one uart adapted to suit smart card interface needs, for asynchronous sc as defined by iso 7816-3. it includes sc clock generation. two serial peripheral interfaces (spi) allow full duplex, synchronous communications with external devices, master or slave operation, max baud rate of 5.5 mb/s. one spi may be used as multimedia card interface.
features summary sta2058 4/20 tw o i 2 c interfaces provide multi-master and slave functions, support normal and fast i 2 c mode (400 khz), 7/10 bit addressing modes. one i 2 c interface is multiplexed with one spi, so either 2 x spi + 1 x i 2 c or 1 x spi + 2 x i 2 c may be used at a time. enhanced interrupt controller supports 32 interrupt vectors, independently maskable, with interrupt vector table for faster response and 16 priority levels, software programmable for each source. up to 2 maskable interrupts may be mapped on fiq. wakeup unit allows exiting from power down modes by detection of an event on two external pins (one is active high and other is active low) or on internal real time clock alarm. usb unit v1.1 compliant, software configurable endpoint setting, usb suspend/resume support high level data link controller (hdlc) unit supports full duplex operating mode, nrz, nrzi, fm0 and manchester modes, and internal 8-bit baud rate generator.
sta2058 pin description 5/20 2 pin description 2.1 logic symbol figure 1. sta2058 teseo symbol avss wen.[1:0] ck ckout csn.[3:0] d[15:0] dbgrqs jtdi jtdo jtck jtms rstinn jtrstn rdn p0.[15:0] p1.[15:0] p2.[15:0] rtcxti rtcxto nstdby_o booten usbdn usbdp v18bkp v18 (2) v33 (7) vss (10) wakeup a[23:0] avdd emi interface power pads clock & reset generai purpose i/o debug jtag port rtc usb pads & wkup pads lfbga144 only gpsdat[1] lfbga144 only sta2058 gpsclk nstdby_i nwakeup gpsdat[0] (lfbga144 only) teseo
system block diagram sta2058 6/20 3 system block diagram figure 2. sta2058 teseo block diagram 39 dp + 8 af 256k flash arm7tdmi cpu 64k ram stc(jtag) arm7 native bus interrupt contr. 12-bit a/d converter timer0 watchdog fully prog. i/o 5 dp uart0 4 af apb bridge2 1 dp 2 af 48 io timer1 4 af emi rtc 2 dp uart1 uart2 uart3 2 af 2 af 2 af 2 af hpgps 16-ch. correlator + emerald dsp [usb] 3 dp hdlc 3 af wakeup 16 af oscill [can0] 2 af vreg 3 dp rccu pll i2c0 2 af i2c1 2 af apb bus apb bridge1 apb bridge3 spi0 4 af apb bus timer2 2 af timer3 4 af 3 dp [can1] 2 af spi1 4 af 5 dp
sta2058 system block diagram 7/20 figure 3. new hpgps 16-ch including emerald dsp 16-bit arm emerald hpgps ip 1023x32 ram a0 1023x32 ram b0 register interface aa da rwa ab db csa csb rwb 2046x32bit ram (*) xbar pram yram xram ybus xbus apb bus isr xbus apb ybus pbus pbus acquisition output data int int int 4 3 (*) maximum memory size addressable by hpgps. the real value depends on the device specs hpgps_eme top 1023x32 ram a1 1023x32 ram b1
system block diagram sta2058 8/20 3.1 package lfbga144 table 2. ball out for lfbga144 package abcdefgh j kl m 1 p0.10/ u1.rx/ u1.tx p2.0/ csn.0 p2.1/ csn.1 vss p2.2/ csn.2 p2.6/ a.22 booten p2.12 p2.13 p2.15 jtdi nc 2 vss rdn p0.11/ u1.tx/ boot.1 v33 p2.3/ csn.3 p2.8 p2.9/ can1_tx jtms jtrstn gpsclk gpsdat1 v33reg_b kp 3 v33 p0.9/ u0.tx/ boot.0 p0.12/ scclk p0.13/ u2.rx/ t2.ocmp a p2.4/ a.20 nc p2.10/ can1_rx jtck gpsdat0 v33 vssreg dbgrqs 4 p0.6/ s1.sclk p0.7/ s1.ssn p0.8/ u0.rx/u0. tx p0.14/ u2.tx/ t2.icapa p2.5/ a.21 vss p2.11 jtdo ck ckout vss vss 5 a.19 wen.1 wen.0 p0.5/ s1.mosi p2.7/ a.23 vss p2.14 nc rtcxto rtcxti wakeup_ pa p0.15/ wakeup 6 p0.3/ s0.ssn/ i1.sda a.15 a.16 a.17 a.18 v33 v18 v18 v18bkp v18bkp vssbkp nstdby_in 7 p0.2/ s0.sclk/ i1.scl p0.1/ s0.mosi/ u3.rx p0.4/ s1.miso vss v18 a.14 d.12 d.1 d.0 nstdby_ o vss18 rstinn 8 a.9 a.10 a.11 a.13 p0.0/ s0.miso/ u3.tx a.0 d.11 p1.12/ cantx avss avss d.3 d.2 9 vss18 v33 a.5 a.6 v33 d.15 d.10 p1.8/ pps d.9 p1.0/ t3.ocmp b/ ain.0 nc avdd 10 a.8 v33 p1.15/ htxd p1.13/ hclk/ i0.scl vss d.14 usbdn p1.7/ t1.ocmp b d.8 p1.5/ t1.icapb p1.1/ t3.icapa/ ain.1 d.4 11 a.7 nc p1.14/ hrxd/ i0.sda p1.10/ usbclk a.2 d.13 usbdp vssio- pll d.5 p1.4/ t1.icapa p1.3/ t3.icapb/ ain.3 avdd 12 a.12 a.4 a.3 p1.9/ prn.11 a.1 p1.11/ canrx nc v33io-pll p1.6/ t1.ocmpa d.7 d.6 p1.2/ t3.ocmpa/ ain.2
sta2058 system block diagram 9/20 3.2 package lqfp64 figure 4. lqfp64 package outline 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10/usbclk p1.9/prn.11 vss p1.12/cantx/usbdn p1.11/canrx/usbdp p1.8/pps p1.7/t1.ocmpa vssio-pll v33io-pll p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 v33reg_bkp vssreg ck p0.15/wakeup rtcxti rtcxto nstdby_in nrstin vssbkp v18bkp v18 vss18 avdd avss p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.10/u1.rx/u1.tx p0.11/u1.tx/boot.1 p0.12/scclk vss p0.13/ u2.rx/t2.ocmpa p0.14/ u2.tx/t2.icapa booten vss v33 jtdi jtms jtck jtdo njtrst gpsdat gpsclk p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx v33 vss p1.15/htxd teseo lqfp64 remapped for bkp supply double bond bw can & usb pads
system block diagram sta2058 10/20 3.3 power supply pins note: v 33 and v 33io-pll are all internally connected. same for v ss and v ssio-pll . all v ss , v ss18 , v ssbkp , av ss pins must be tied together to the common ground plane, taking care of noise filtering, especially on av ss table 3. power supply pins symbol i/o function lqfp 64 lfbga144 v 33 - digital supply voltage for i/o circuitry (3.3 volt) 9, 51 d2,a3,k3,f6,b9 , e9,b10 v ss - digital ground for i/o circuitry 4, 8, 44, 50, 59 d1,a2,f4,l4,m 4, f5, d7,e10 v 33io-pll - digital supply voltage for i/o circuitry and for pll reference (3.3v) 38 h12 v ssio-pll - digital ground for i/o circuitry and for pll reference 39 h11 v 33reg_b kp - digital supply voltage for backup block i/o circuitry and for ballast i/o (3.3v) 17 m2 v ssreg - digital ground for ballast i/o 18 l3 v 18 - digital supply voltage for co re circuitry (1.8 volt): when using the internal voltage regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 10 f (tantalum, low series resistance) + 33nf (ceramic) shall be connected between these pins and v ss18 to guarantee on-chip voltage stability. 27, 58 g6, h6,e7 v ss18 - digital ground for core circuitry 28, 57 a9,l7 v 18bkp - digital supply voltage for backup block (rtc, oscillator, wake-up controller - 1.8 volt): when using the internal voltage regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 1 f shall be connected between this pin and v ssbkp to guarantee on-chip voltage stability. 26 j6,k6 v ssbkp - digital ground for backup logic 25 l6 av dd - analog supply voltage for the a/d converter 29 m9, m11 av ss - analog supply ground for the a/d converter 30 j8,k8
sta2058 electrical characteristic 11/20 4 electrical characteristic 4.1 dc electrical characteristic v 33 = 3.3 v 10 %, t a = -40 / 85 c unless otherwise specified. table 4. dc electrical characteristic symbol parameter test conditions value min. typ. max. unit v ih input high level cmos with or w/o hysteresis 0.7v 33 v input high level p0.15 (wakeup) only 1.8 v v il input low level cmos with or w/o hysteresis 0.3v 33 v input low level p0.15 (wakeup) only 0.7 v v hys input hysteresis cmos schmitt trigger 0.4 0.8 1.2 v input hysteresis schmitt trigger p0.15 (wakeup) only 0.3 0.5 v v oh output high level high current pins push pull, i oh = 8ma v 33 -0.8 output high level standard current pins push pull, i oh = 4ma v 33 -0.8 v ol output low level standard current pins push pull, i oh = 8ma 0.4 v push pull, i oh = 4ma 0.4 v r wpu weak pull-up resistor measured at 0.5v 33 100 k r wpd weak pull-down resistor measured at 0.5v 33 100 k
electrical characteristic sta2058 12/20 4.2 ac electrical characteristics note: iddrun is the consumption in applications exploiting the full performances of the core. a typical gps application would run at 33mhz, at the maximum frequency (66mhz) the power consumption is iddrun = 150 ma (typ). in wfi mode the vreg and flash are on to guarantees the minimum interrupt response time. 4.3 nrstin input filter characteristics v 33 = 3.3 v 10 %, t a = -40 / 85 c unless otherwise specified. table 5. ac electrical characteristics v 33 = 3.3 v 10 %, t a = 27 c unless otherwise specified. symbol mode system clock value unit min. typ. max. i ddrun run mode 33 mhz system clock 60 ma i ddwfi wfi mode 1 mhz system clock 5 ma i ddlp lpwfi mode 32 khz system clock 300 a i ddstp stop mode main vreg off, flash in power-down 200 a i ddsb1 standby_1 mode lp vreg and 32khz osc on 15 30 a i ddsb0 standby_0 mode lp vreg, lvd, 32khz osc bypassed 3 10 a table 6. ac electrical characteristics v 33 = 3.3 v 10%, t a = -40 / 85 c unless otherwise specified. symbol mode system clock value unit min. typ. max. f cpu cpu max frequency executing from ram or emi 66 mhz f max flash max frequency executing from flash 60 mhz table 7. nrstin input filter characteristics symbol mode system clock value unit min. typ. max. t fr nrstin input filtered pulse 100 ns t nfr nrstin input not filtered pulse 1.2 s
sta2058 electrical characteristic 13/20 4.4 flash electrical characteristics v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. note: c 0 : t a = 85 c after 0 cycles c max : t a = 85 c after max number of cycles table 8. flash program/erase characteristics 1 symbol parameter test conditions value unit typ max (c 0 )max (c max ) t pw word program 40 s t pdw double word program 60 s t pb0 bank 0 program (256k) double word program 1.6 2.1 4.3 s t pb1 bank 1 program (16k) double word program 130 170 300 ms t es sector erase (64k) not preprogrammed preprogrammed 2.3 1.9 4.0 3.3 4.9 4.1 s t es sector erase (8k) not preprogrammed preprogrammed 0.7 0.6 1.1 1.0 1.36 1.26 s t es bank 0 erase (256k) not preprogrammed preprogrammed 8.0 6.6 13.7 11.2 17.2 14.0 s t es bank 1 erase (16k) not preprogrammed preprogrammed 0.9 0.8 1.5 1.3 1.87 1.66 s t rpd recovery from power-down 20 s t psl program suspend latency 10 s t esl erase suspend latency 300 s table 9. flash program/erase characteristics 2 symbol parameter conditions value unit min typ max endurance 10 kcycles endurance (bank1 sectors) 100 kcycles data retention 20 ye a r s t esr erase suspend rate min time from erase resume to next erase suspend 20 ms
electrical characteristic sta2058 14/20 4.5 oscillator electrical characteristics v 33 = 3.3 10 %, t a = -40 / 85 c unless otherwise specified. figure 5. crystal oscillator and resonator 4.6 adc electrical characteristics v 33 = 3.3 10%, a vdd = 3.3v 10%, t a = -40 / 85 c unless otherwise specified. c l c l rtcxti rtcxto r s rtcxti rtcxto device device table 10. oscillator electrical characteristics symbol parameter test conditions value unit min typ max g m oscillator transconductance 8 a/v t stup oscillator startup time stable v dd 2.5 s table 11. adc electrical characteristics symbol parameter test conditions value unit min typ max res resolution sinewave with v in amplitude 12 bits v in input voltage range 0 2.5 v f mod modulator oversampling frequency 2.1 mhz ibw input bandwidth f mod /40 96 khz n ch number of input channels 4 n pbr passband ripple 0.1 db sinad s/n and distortion 56 63 db thd total harmonic distortion 60 74 db
sta2058 electrical characteristic 15/20 4.7 pll electrical characteristics v 33 = 3.3 10 %, v 33iopll = 3.3 10 %, t a = -40 / 85 c unless otherwise specified. 4.8 lvd electrical characteristics v 33 = 3.3 10 %, t a = -40 / 85 c unless otherwise specified. z in input impedance f mod = 2 mhz 1 m c in input capacitance 5 pf i adc power consumption t a =27 c 2.5 3.0 ma i stby standby power consumption t a =27 c 1 a table 11. adc electrical characteristics (continued) symbol parameter test conditions value unit min typ max table 12. pll electrical characteristics symbol parameter test conditions value unit min typ max t pll1 pll reference clock fref_range=0 1.5 3.0 mhz t pll2 pll reference clock fref_range=1 mx[1:0]=?00? or ?01? 3.0 8.25 mhz t pll3 pll reference clock fref_range=1 mx[1:0]=?10? or ?11? 3.0 6 mhz t lock pll lock time fref_range=0 stable input clock stable v 33iopll , v 18 300 s t lock pll lock time fref_range=1 stable input clock stable v 33iopll , v 18 600 s t jitter pll jitter (peak to peak) t pll = 4 mhz, mx[1:0]=?11? global output division=32 (output clock=2 mhz) 0.7 2 ns table 13. lvd electrical characteristics symbol parameter test conditions value unit min typ max t lv d lvd threshold main and lp lvd?s 1.3 v vvlpreg - t lv d main regulator off 50 mv
electrical characteristic sta2058 16/20 4.9 gps performances v 33 = 3.3 10 %, t a = 27 c, unless otherwise specified table 14. gps performances symbol parameter test conditions value unit min typ max ttff reacquisition 50%, -130dbm, fu 2ppm, tu 2 , p u 3 0 k m <1 s hot start <2.5 s warm start <34 s cold start <39 s accuracy autonomous cep 50%, 24hr static at - 130dbm 2m sensitivity acquisition (warm start) with external lna -146 dbm tracking -159 dbm
sta2058 package information 17/20 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 6. lqfp64 mechanical data and package dimensions outline and mechanical data a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.08mm dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.20 0.0066 0.0086 0.0106 0.0079 c 0.09 0.0035 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 7.50 0.295 e 0.50 0.0197 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 7.50 0.295 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0393 k 0? (min.), 3.5? (min.), 7?(max.) ccc 0.080 0.0031 lqfp64 (10 x 10 x 1.4mm) 0051434 f ccc
package information sta2058 18/20 figure 7. lfbg144 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.21 1.70 0.0476 0.0669 a1 0.21 0.0083 a2 1.12 0.0441 b 0.35 0.40 0.45 0.0138 0.0157 0.0177 d 9.85 10.0 10.15 0.3878 0.3937 0.3996 d1 8.80 0.3465 e 9.85 10.0 10.15 0.3878 0.3937 0.3996 e1 8.80 0.3465 e 0.80 0.0315 f 0.60 0.0236 ddd 0.10 0.0039 eee 0.15 0.0059 fff 0.08 0.0031 lfbga144 l ow profile f ine pitch b all g rid a rray 7163385 d body: 10 x 10 x 1.7mm
sta2058 revision history 19/20 6 revision history table 15. document revision history date revision changes 23-apr-2007 1 initial release. 25-jun-2007 2 added features summary, pin description, electrical characteristics and packages information. 19-mar-2009 3 updated table 1: device summary on page 1 . updated ecopack description in section 5: package information on page 17 .
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